This is a self-study course for learning the Verilog Hardware
Description Language. There are 9 chapters in the course:
- Introduction, Hierarchy, and Modelling Structures
- Syntax, Lexical Conventions, Data Types, and Memories
- Expressions and Simulation Mechanics
- Gate Level Modelling
- Behavioral and Register Transfer Level Modelling
- Advanced Features
- Coding Style
- Debugging Verilog Models
- The Programming Language Interface
Each chapter has a number of topics and
subsections which you visit by moving around in hypertext.
The course is free, but you must first register.
Click the Table of Contents button to begin.
- If you cannot see the animation above you should download the Flash plug-in before you begin.
- If you are a new user, please click "How to Take this Course" at the Table of Contents.
- Send all feedback related to this course to Verilog@verilog.com.
Copyright © 1996-2002 by John Sanguinetti
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