This is a self-study course for learning the Verilog Hardware Description Language. There are 9 chapters in the course:

  • Introduction, Hierarchy, and Modelling Structures
  • Syntax, Lexical Conventions, Data Types, and Memories
  • Expressions and Simulation Mechanics
  • Gate Level Modelling
  • Behavioral and Register Transfer Level Modelling
  • Advanced Features
  • Coding Style
  • Debugging Verilog Models
  • The Programming Language Interface

Each chapter has a number of topics and subsections which you visit by moving around in hypertext.

The course is free, but you must first register.

Note: This course does not work with Internet Explorer version 6.0.2900. It works great with FireFox which you can get by clicking on the FireFox logo below.

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